Hardware Description Language: Verilog

The technology of translating a given digital design task into digital logic has
undergone many changes. The 1970s and 1980s witnessed a schematic design
approach. From the mid-1990s onward, digital design has been done using
hardware description language (HDL). HDLs came into existence to help the
designer with the simulation of digital logic. The availability of synthesis tools that
convert HDL logic to FPGA primitives has made HDL the digital design entry
method of choice. Given the fact that HDLs started out primarily as a simulation
language, there are many HDL constructs that cannot be synthesized to digital
logic. This chapter will focus on the synthesizable subset of constructs of Verilog
HDL. Describing a digital design using HDL is usually the first step toward
prototyping the design using FPGA. The rest of the book will use Verilog
constructs introduced in this chapter to create digital designs for interfacing,
networking, signal conditioning and motor control applications. Verilog is a vast
language, and it is beyond the scope of this chapter and book to dwell on all the
nuances of the language.